VLSI physical design: from graph partitioning to timing closure

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Material type: Text

TextPublication details: Springer -- Switzerland -- 2022Edition: 2nd edDescription: xvii, 317pISBN:

9783030964177

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DDC classification:

621.395 KAH

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Item type	Current library	Collection	Call number	Status	Date due	Barcode
Books	Mahindra University VNLRC General Stacks	ECE	621.395 KAH (Browse shelf(Opens below))	Checked out	26/05/2026	20785

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Previous	621.395 GEI VLSI design techniques for analog and digital circuits	621.395 GEI VLSI design techniques for analog and digital circuits	621.395 GEI VLSI design techniques for analog and digital circuits	621.395 KAH VLSI physical design: from graph partitioning to timing closure	621.395 KRO Introduction to formal hardware verification	621.395 LEE Verilog coding for logic synthesis	621.395 PUC Basic VLSI design	Next

- 1 Introduction.

- 2 Netlist and System Partitioning.

- 3 Chip Planning.

- 4 Global and Detailed Placement.

- 5 Global Routing.

- 6 Detailed Routing.

- 7 Specialized Routing.

- 8 Timing Closure.

- A Solutions to Chapter Exercises.

- B Example CMOS Cell Layouts.

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